MARVELL 88E1512 DRIVER DOWNLOAD

To contact Marvell Sales, please submit your inquiry via request for information below. I enable eth0 and see transactions on the MDIO bus. We have a custom board with a Zynq using two Marvell 88e PHYs for dual ethernet and have not been able to get eth1 up and running on xilinx-linux eth0 works fine. With linux this indeed is a problem, when doing it correctly in devicetree then lots of errors come during boot, claiming PHY 0 is invalid, then PHY 0 is enabled, and working, and the second PHY with address 1 valid address remains not configured and is fully not accessible. Driver Downloads Download the latest Marvell drivers for your specific device or application. We changed our HW definition to make that a GPIO, and we take it out of reset in the early board init function of u-boot. Add the phy handle to the gem sections:

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I have tried that previously and once againt to verify. Check the 88e152 pin to the PHYs. This has been tested on Zynq Ultrascale with a Daughter card.

88EA0-NNP2I Marvell | Ciiva

I have tried the current xilinx-linux git repo, and the patch is not in marvfll repo, nor is the patch applicable to that repo. I will dig into the kernel code to see if there is a workaround.

Could you explain how to implement Xilinx provided patch at each these different steps? Hoping to get a pre-release of the Cadence GEM rev 0x at 0xeb irq ChromeFirefoxInternet Explorer 11Safari.

Access comprehensive product specifications for Marvell's family of Transceivers products:. Not sure about the dsa or link. There 88e112 a little communication confusion with Xilinx. We verified that before trying it in the kernel.

It's not being released in the petalinux Please upgrade to a Xilinx. This seems to make sense, as all the other 88e512 phy configurations I see have PHY addresses that aren't zero. It's likely that a hardware workaround in the fabric is easier to implement than digging into the Linux core software.

It's almost as if the default config of the PHY is enough to pass data to the eth1 interface even though it hasn't been configured. Flipping bit 1 would translate the address of the two PHYs to 2 and 3 instead of 881512 and 1.

Alaska Gigabit Ethernet PHYs Transceivers As Ethernet technology becomes more prevalent in everyday mainstream applications such as IP phones, gaming consoles, PDAs, printers, and traditional home or corporate network connections, the demand for energy efficiency and advanced process technologies increases.

With the Msrvell family, Marvell delivers a new class of Gigabit PHYs designed to meet the demands of next-generation green networks.

Alaska Gigabit Ethernet PHYs Transceivers

To contact Marvell Sales, please submit your inquiry via request for information below. If you want to achieve great things, then we want to talk with you.

We changed our HW definition to make that a GPIO, and we take it out of reset in the early board init function of u-boot. If they both operate at 2. Give Kudos to a post which you think is magvell and reply oriented.

PHY Transceivers, Alaska X Gigabit Ethernet PHY - Products - Marvell

Additional features of the Alaska GbE PHYs include a high-level of integration in thermally-efficient packages that optimize PCB real estate and enable fan-less heat-sink-less designs. Quickly and easily view product specs, compare various solutions, and print out select product information.

We aren't using petalinux, but the kernel config stuff all looks the same. Another question if I may, what about the dsa part in the tree, isn't it required? However, I don't see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth1: According to a Xilinx FAE: I'm looking for some insight that I'm missing, or some other clue to indicate why the kernel drivers can't detect PHY1 at address 1 correctly.

Cadence GEM rev 0x at 0xec irq